1. Field of the Invention
The present invention relates to a technique for controlling the ON resistance of a pullup transistor which is provided in an input/output buffer circuit.
2. Description of the Background Art
FIG. 12 is a circuit diagram showing a conventional input buffer circuit which comprises a pullup transistor.
A PMOS transistor Q.sub.2 has a drain which is connected to an output terminal P.sub.o, a source which is connected to a high potential power source V.sub.DD, and a gate which is connected to an input terminal P.sub.i. An NMOS transistor Q.sub.3 has a drain which is connected to the output terminal P.sub.o, a source which is connected to a low potential power source V.sub.SS (ground in this case), and a gate which is connected to the input terminal P.sub.i. Namely, the MOS transistors Q.sub.2 and Q.sub.3 form a CMOS inverter 11, which has a transition voltage V.sub.IT (V.sub.DD &gt;V.sub.IT &gt;V.sub.SS).
On the other hand, a PMOS transistor Q.sub.1 is connected to the input terminal P.sub.i as a pullup transistor. This PMOS transistor Q.sub.1 has a drain which is connected to the input terminal P.sub.i, a source which is connected to the power source V.sub.SS, and a gate which is connected to the power source V.sub.DD. The potential of the power source V.sub.DD is hereinafter also indicated by V.sub.DD. This also applies to the other power source V.sub.SS.
The conventional input buffer circuit is thus formed by the inverter 11 and the PMOS transistor Q.sub.1, and two types of logical levels are inputted in the input terminal P.sub.i from a front stage circuit. This can equivalently be regarded as that a front stage output impedance Z.sub.o and a square-wave oscillator outputting a potential V.sub.i (V.sub.i takes binary levels) are connected to the input terminal P.sub.i.
The operation of the input buffer circuit shown in FIG. 12 is now described.
First, consider that the input terminal P.sub.i enters a high impedance state (hereinafter referred to as "Z state"), i.e., the front stage output impedance Z.sub.o is extremely increased. Such a state is caused when the front stage circuit has an open drain type output part with a plurality of pulldown transistors Q.sub.d as shown in FIG. 14 and all pulldown transistors Q.sub.d are converted from ON states (conducting states) to OFF states (cutoff states), for example. Referring again to FIG. 12, the PMOS transistor Q.sub.1, which is a pullup transistor, is regularly in an ON state since its gate is connected with the power source V.sub.SS, and connects the input terminal P.sub.i to the power source V.sub.DD with its ON resistance. Thus, the potential of the input terminal P.sub.i is set at a high logical level. Since a through current is most increased in the vicinity of the transition voltage V.sub.IT of the inverter 11, the potential of the input terminal P.sub.i is controlled to not be around the transition voltage V.sub.IT of the inverter 11, thereby avoiding breakage of the MOS transistors Q.sub.2 and Q.sub.3 caused by flow of the through current to the MOS transistors Q.sub.2 and Q.sub.3. Namely, the PMOS transistor Q.sub.2 is brought into an OFF state and the NMOS transistor Q.sub.3 is brought into an ON state, to bring the potential of the input terminal P.sub.i to a high logical level. At this time, the output terminal P.sub.o is connected with the power source V.sub.SS, to output a low logical level.
When a logical level V.sub.H which is higher than the transition voltage V.sub.IT is inputted in the input terminal P.sub.i, the PMOS transistor Q.sub.2 enters an OFF state and the NMOS transistor Q.sub.3 enters an ON state. Therefore, the output terminal P.sub.o is connected with the power source V.sub.SS, to output a low logical level.
When a logical level V.sub.L which is lower than the transition voltage V.sub.IT is inputted in the input terminal P.sub.i, on the other hand, the PMOS transistor Q.sub.2 enters an ON state and the NMOS transistor Q.sub.3 enters an OFF state. Therefore, the output terminal P.sub.o is connected with the power source V.sub.DD, to output a high logical level.
Since the PMOS transistor Q.sub.1 connects the input terminal P.sub.i to the power source V.sub.DD with its ON resistance, the potential of the input terminal P.sub.i is determined by resistance division of the front stage output impedance Z.sub.o and this ON resistance. When a high logical level transition voltage of the overall input buffer circuit shown in FIG. 12 is set as V.sub.IH (&gt;V.sub.IT) and a low logical level transition voltage is set as V.sub.IL (&lt;V.sub.IT), therefore, the ON resistance is so determined that the potential of the input terminal P.sub.i becomes higher than the transition voltage V.sub.IT if the potential V.sub.i of the square wave oscillator satisfies V.sub.i &gt;V.sub.IH while the potential of the input terminal P.sub.i becomes lower than the transition voltage V.sub.IT if the potential V.sub.i satisfies V.sub.i &lt;V.sub.IL. In more concrete terms, this is implemented by properly designing the transistor size of the PMOS transistor Q.sub.1.
FIG. 13 is a timing chart showing such a case that the above operations are continuously performed. It is assumed here that the potential V.sub.i of the oscillator takes either the potential V.sub.DD or V.sub.SS, for the purpose of simplification. In advance of a time t.sub.1, a high logical level (potential V.sub.DD in this case) is inputted in the input terminal P.sub.i (this state is hereinafter referred as "state H"), and a low logical level (potential V.sub.SS in this case) is outputted at the output terminal P.sub.o (this state is hereinafter referred to as "state L"). Between the time t.sub.1 and a time t.sub.2, a low logical level (V.sub.C) is inputted in the input terminal P.sub.i, and a high logical level (potential V.sub.DD in this case) is outputted at the output terminal P.sub.o. The potential V.sub.C is slightly higher than the potential V.sub.i (=V.sub.SS) of the oscillator. This is because the potential difference V.sub.DD -V.sub.SS is resistance-divided by the front stage output impedance Z.sub.o and the ON resistance of the NMOS transistor Q.sub.1, as hereinabove described. After the time t.sub.2, the front stage output impedance Z.sub.o is increased in a Z state, and the potential of the input terminal P.sub.i is raised to the potential V.sub.DD by the PMOS transistor Q.sub.1, while the potential of the output terminal P.sub.o reaches the potential V.sub.SS.
Such a pullup transistor is also employed in an output buffer circuit. FIG. 15 is a circuit diagram showing a conventional output buffer circuit which comprises a pullup transistor.
A PMOS transistor Q.sub.4 has a drain which is connected to an output terminal P.sub.oo, a source which is connected to a power source V.sub.DD, and a gate which is connected to an output end of a NAND gate G3. An NMOS transistor Q.sub.5 has a drain which is connected to the output terminal P.sub.oo, a source which is connected to a power source V.sub.SS, and a gate which is connected to an output end of a NOR gate G4. Namely, the MOS transistors Q.sub.4 and Q.sub.5 form a tristate type CMOS inverter 21.
Gates G2, G3 and G4 form a tristate type control circuit 20. The gate G2 is an inverter, whose input end is connected to a drive allowing input terminal P.sub.i1. First and second input ends of the NAND gate G3 are connected to an output end of the gate G2 and a drive selecting input terminal P.sub.i2 respectively. First and second input ends of the NOR gate G4 are connected to the drive allowing input terminal P.sub.i1 and the drive selecting input terminal P.sub.i2 respectively.
On the other hand, a PMOS transistor Q.sub.6 is connected to the output terminal P.sub.oo as a pullup transistor. This PMOS transistor Q.sub.6 has a drain which is connected to the output terminal P.sub.oo, a source which is connected to the power source V.sub.SS, and a gate which is connected to the power source V.sub.DD.
The control circuit 20, the inverter 21 and the PMOS transistor Q.sub.6 form an output buffer circuit A.sub.0. Further, n output buffer circuits having similar structures are connected in common with the output terminal P.sub.oo. The output terminal P.sub.oo transmits signals to a next stage circuit. An input buffer circuit 40 of the next stage circuit has a transition voltage V.sub.IT.
The operation is now described.
In order to select one from the plurality of output buffer circuits A.sub.0 to A.sub.n, a low logical level is inputted in the drive allowing input terminal P.sub.i1 (state L). It is assumed here that such a low logical level is inputted in the drive allowing input terminal P.sub.i1 of the output buffer circuit A.sub.0, to select the output buffer circuit A.sub.0.
When a high logical level is inputted in the drive selecting input terminal P.sub.i2 of the output buffer circuit A.sub.0 (state H) in this case, the output of the NAND gate G3 enters a state L and the PMOS transistor Q.sub.4 enters an ON state, while the output of the NOR gate G4 also goes to a low logical level and the NMOS transistor Q.sub.5 enters an OFF state. Consequently, a high logical level is outputted at the output terminal P.sub.oo (state H). When a low logical level is inputted in the drive selecting input terminal P.sub.i2 (state L), on the other hand, the PMOS transistor Q.sub.4 enters an OFF state while the NMOS transistor Q.sub.5 enters an ON state, and a low logical level is outputted at the output terminal P.sub.oo (state L).
When none of the output circuits A.sub.0 to A.sub.n is selected, i.e., when the drive selecting input terminal of every one of the output circuits A.sub.0 to A.sub.n is in a state H, the output of the NAND gate G3 enters a state H and the PMOS transistor Q.sub.4 enters an OFF state in each of the output buffer circuits A.sub.0 to A.sub.n. At the same time, the output of the NOR gate G4 enters a state L, and the NMOS transistor Q.sub.5 also enters an OFF state. Consequently, the output (drain terminal common junction) of the inverter 21 itself enters a Z state, to generate no output. However, the output terminal P.sub.oo enters a state H since the PMOS transistor Q.sub.6 is regularly in an ON state due to the potential V.sub.SS applied to its gate. Thus, a floating state of the output terminal P.sub.oo is so avoided that it is possible to avoid flow of a through current even if the next stage input buffer circuit 40 has a CMOS structure similarly to the inverter 11 shown in FIG. 12.
If the output terminal P.sub.oo is in a state L when the output circuit A.sub.0 is selected, i.e., the drive allowing input terminal P.sub.i1 is in a state L, the PMOS transistor Q.sub.4 is in an ON state (the NMOS transistor Q.sub.5 is in an OFF state), and the potential of the output terminal P.sub.oo in the state L is determined by resistance division of the ON resistance of the PMOS transistor Q.sub.6 and the ON resistance of the PMOS transistor Q.sub.4 since the PMOS transistor Q.sub.6 is regularly in an ON state. Thus, the PMOS transistor Q.sub.6 is so designed that the relation between a high logical level transition voltage V.sub.OH and a low logical level transition voltage V.sub.OL of each of the output circuits A.sub.0 to A.sub.n and the transition voltage V.sub.IT of the input buffer circuit 40 is V.sub.OH &gt;V.sub.IT &gt;V.sub.OL.
Since the conventional input and output buffer circuits have the aforementioned structures, it is possible to avoid a through current in the inverter 11 of the input buffer circuit when the output part of the front stage circuit enters a Z state, while a through current in an inverter of the next stage circuit can be avoided in the output buffer circuit.
However, since the PMOS transistors Q.sub.1 and Q.sub.6, which are pullup transistors, are regularly in ON states in order to attain the respective effects, unwanted currents flow to the same to cause undesired power consumption.
As to the input buffer circuit, a current inevitably flows to the PMOS transistor Q.sub.1 when a low logical level is inputted in the input terminal P.sub.i in FIG. 12, to consume undesired power.
As to the output buffer circuit, on the other hand, a current inevitably flows to the PMOS transistor Q.sub.6 when a low logical level is outputted at the output terminal P.sub.oo in FIG. 15, to consume undesired power.